Bringing Together the IP Community

December 14, 2017
9am – 7pm
Santa Clara Convention Center

REUSE 2017 will again bring the global IP community together, this time at the Santa Clara Convention Center in the center of Silicon Valley. Here an even greater diversity of suppliers will be promoting their products in a fair and balanced showcase. REUSE will also provide an open forum for communication and networking within our industry.


Ted Miracco

CEO, SmartFlow Compliance Solutions

    Heather Monigan

    Program Director & Technology Strategist, Intel Corporation

      Hong Hao

      Sr. Vice President, Foundry Business - Samsung


        Vice President of Sales, CAST


          Director, Solutions Architecture, Flex Logix

            WARREN SAVAGE

            General Manager, Silvaco

              John Heinlein, Ph.D.

              Vice President, Strategic Initiatives, Arm

                Timothy Saxe, Ph.D.

                Senior VP of Engineering and CTO, QuickLogic

                  STEPHEN FAIRBANKS

                  Co-Director, Certus Semiconductor

                    Brian Gardner

                    V.P. of Business Development, True Circuits, Inc.

                      Steve Mensor

                      VP of Marketing, Achronix Semiconductor Corporation

                        Mike Noonen

                        Silego Technology

                          Dr. Naveed Sherwani

                          President and CEO, SiFive

                            John Blyler

                            Editorial Director, Semi-IP Systems at JB Systems

                              Michael Wishart

                              CEO, efabless

                                Lucio Lanza

                                Managing Director, Lanza Tech Ventures

                                  Andrew Cole

                                  Vice President, Silicon Creations

                                    Jim Bruister

                                    Director Digital Systems, Silvaco

                                      Itsu Wang

                                      Senior Director, Asia Sales & Marketing, QuickLogic


                                        Keynote: High Tech Companies Dealing With IP Theft Must Take Action to Protect Themselves - SmartFlow Compliance Solutions

                                        A 2017 report by the Commission on the Theft of American Intellectual Property estimates that the annual cost of IP theft to the U.S. exceeds $225 billion, translating to 1.25 percent of our economy, but may be as high as $600 billion when taking into account unreported/unmeasured types of IP theft. The estimated value is difficult to accurately measure due to the ease with which software can be transferred via the internet and duplicated without licensing or royalties. The cost of trade secret theft is also difficult to assess because companies may not even be aware that their IP has been stolen, nor are they motivated to report their losses once discovered. In the past, semiconductor companies experiencing IP theft have viewed it as a forgone conclusion and have had little means to fight back. But things are changing. New laws have been put in place that do more to protect the theft of IP, both in the U.S. and Europe and there are new technologies that can be leveraged to document designs. License owners can no longer afford to ignore the fact that their IP is being stolen or being used out of compliance with the intended licensing. Intellectual property is the bedrock of our high-tech economy and there has never been a more important time to protect IP. As more and more fabless semiconductor companies emerge throughout the world, it is great time to look at how we can best protect their designs and make sure the companies that innovate can benefit from their innovations on a fair playing field.

                                        Ted Miracco

                                        Embedding FPGAs will make microcontrollers and SoCs more flexible and powerful. Reconfigurable accelerators can accelerate the main workloads by 30+ times faster than a processor. Programmable I/O enables implementation of as many and whatever type of serial I/O required. And offloading repetitive monitoring tasks to embedded FPGA can increase battery life for power-sensitive applications by 2-3x. Tony will show details and examples.

                                        Tony Kozaczuk

                                        Reliable Silicon and Software IP with the right features is key for the timely design of today's complex automotive electronics. What used to be science fiction is now science fact: cars connect to the internet, drive on their own, alert the driver to and help avoid hazards, and offer rich infotainment systems with smartphone integration. Here we will discuss how the right Silicon IP helps automotive engineers achieve demanding design goals faster and with less risk. Examples come from CAST's Automotive IP product line, which covers today's co-existing interconnect technologies—ranging from LIN and SENT to CAN-FD and Automotive Ethernet—and also provides solutions for the low-latency, high- quality processing, compression, and display of automotive image and video content.

                                        Meredith Lucky

                                        Developing a chip takes time, money and effort. So when developing a chip, designers want the assurance that they are using the best, most proven IP available. So what does it take to create CPUs that are deployed in thousands of different designs and shipped in billions of different chips? This presentation will outline some of the many activities that Arm undertakes to create CPUs, the importance of having such a broad ecosystem, and how Arm is making it even easier for designers to get access to Arm processors for IoT.

                                        John Heinlein, Ph.D.

                                        What does a shopper of IP Ecosystem expect of a commercial IP provider? What do customers expect in this constantly changing world? What does the future possibly hold and how can smaller IP providers stay competitive as the future evolves?

                                        Heather Monigan

                                        As the automotive supply chain relies ever more on 3rd-party IP, the cost associated with ISO 26262 certification for semiconductor companies is increasingly expensive and complicated. In this session we will discuss the use of IP fingerprinting as a means for companies to reduce their certification costs and risks associated with incorporating IP into the automotive designs.

                                        Warren Savage

                                        For years now system designers have leveraged standalone FPGAs to augment existing designs in order to get to market first. In the early days, FPGAs with useful gate counts required a whole die to implement. Today, FPGAs with useful gate counts can fit in a few square millimeters, which makes it practical to integrate SoCs and FPGAs in one device. And that means you can build SoC platforms where the standard part is implemented in fixed logic and the differentiated part is implemented as an embedded FPGA. This approach allows SoC design to be leveraged into different market segments and new market segments by programming the FPGA portion – which doesn’t require a new layout, new physical design verification or new masks.

                                        Timothy Saxe, Ph.D.

                                        In wide chip interfaces like DDR, HBM and ONFI, it can be challenging to synthesize and connect high-frequency controllers to the PHY hard macros. Clock trees can be expansive, pushing tools to their limits, and often multiple clock domains are needed. Jitter can also be an issue on long paths. We will show how True Circuits PLL and DLL IP is being used by multiple customers to build ONFI and HBM subsystems in advanced TSMC process nodes, and discuss the tradeoffs and timing budget concerns among different timing architectures. In addition, we will explain how source-synchronous signaling is used in our DDR PHY to ease timing closure, and to allow the memory controller to be synthesized for high-frequency operation, which reduces its size and lowers its latency. By using a soft IP "shim" between the memory controller and PHY, the memory controller only needs a single localized clock tree, reducing mismatch and jitter. The long routes between the soft shim and the PHY hard macros are source-synchronous, so data/strobe groups need only be roughly matched, something easily accomplished by place and route tools.

                                        Brian Gardner

                                        Open innovation, open source and connected community revolutionized the software industry.  Hardware followed suit, led by a grassroots movement of “makers” and powered by Arduino and Raspberry Pi. The semiconductor and IP industry is now beginning to embrace the same principles that drove these industries.  Our panel will explore the specific trends taking hold and the pioneering companies and innovators that are leading the charge.

                                        Mike Noonen | Michael Wishart | Dr. Naveed Sherwani | John Blyler

                                        Achronix SpeedcoreTM eFPGA IP has brought the power and flexibility of programmable logic to ASICs and SoCs. Customers can integrate a Speedcore eFPGA into an SoC for high-performance, compute-intensive and real-time processing applications such as AI, machine learning, 5G wireless, networking and automotive. Speedcore custom blocks dramatically increase the eFPGA performance by allowing customers to define custom functions that can be added as additional blocks in the eFPGA fabric, alongside the traditional building blocks of LUTs, RAMs, and DSPs. This results in significant reduction in the eFPGA die size area, which in-turn reduces silicon costs and power consumption.

                                        Steve Mensor

                                        In this talk, we will take a brief look at the semiconductor industry landscape and trends from a foundry’s perspective. We will discuss the underlying technology challenges and future trends, and how these trends will challenge the semiconductor IP and product designs.

                                        Hong Hao
                                        SPI vs SPI - Silvaco

                                        The presentation will discuss why Serial Flash chips are used in many products and how they compare to parallel flash devices in similar applications. I will discuss the advantages and some of the disadvantages. I will explore how Silvaco’s SPI, QSPI and Octal SPI IP Cores can be used with SPI, QSPI and Octal SPI Flash Memories in microprocessor based SOCs and systems.

                                        Jim Bruister

                                        As if developing first time right IP in 7nm were not difficult enough, ensuring this IP is sufficiently reliable and safe for automotive applications adds a new dimension. This talk provides an overview of the additional design work, verification and reliability calculations layered on top of a standard PLL IP development plan and how the results are documented. It also provides a summary of the Design review materials, ISO26262-compliant FMEDA and ASIL-B/C Safety Manual documents usually required in such cases, and some methods that can be used to ensure PLLs are functioning as intended. The paper also provides a summary of an AEC_Q100 pre-qualification plan that can be used with samples from two MPW wafers to lower the risk that an end product including the tested IP fails final product AEC_Q100 reliability testing of 2700 product samples.

                                        Andrew Cole

                                        Standards have always been a sweet spot for IP, and the availability of CAST’s GZIP and GUNZIP have found traction due to complete interoperability with software implementations. ASIC and FPGA designs incorporating the GZIP cores provide lossless compression equivalent to software while providing higher throughput and low-latency for even demanding in-line data server applications. A look at real-world implementations and IP performance in several technologies will be presented.

                                        Meredith Lucky

                                        IO and ESD design and test in the semiconductor industry has been a relatively stable art for the most of the 1990’s and 2000’s. In the last 10 years, however, we have seen emerging and advancing technologies in both the processes and the packaging options that are having dramatic impacts on ESD and IO Library design and architecture. Beyond just FinFet and Hybrid SOI/Bulk processes, we have Thru-Silicon Via’s, 2D, 2.5D and 3D packaging; Low Voltage CMOS processes integrating High-Voltage BCD technologies, more aggressive packages such as Chip Scale Packaging (CSP) and Wafer Level Chip Scale Packages (WLCSP) technologies, couple all these with the fact that advancing processes have become ever more delicate in terms of reliability and ESD susceptibility, and then we want to put more of these into automotive and aerospace electronics.. and ESD and Reliability is now a big challenge. Organizations are also releasing new standards on age old practices! What is 2-Pin HBM? Do I need 1kV HBM or 2kV HBM? What about qualifying sensitive consumer electronics for automotive environments? This presentation will cover the changing landscape of modern IO design, ESD testing and Reliability testing, with an emphasis on practical approaches and pragmatic understanding.

                                        Stephen Fairbanks

                                        Embedded FPGA (eFPGA) technology is redefining the SoC landscape by providing the developers of such devices with capabilities previously only available in discrete FPGA ICs. The post-manufacturing design flexibility inherent in FPGA technology is now enabling SoC developers to make late cycle design changes to fix bugs, add features, address rapidly changing standards or competitive landscapes, or to address highly fragmented markets requiring different feature sets. The net result of this capability is lower development costs, faster time to market, greater time in market, greater degrees of product differentiation, higher revenues, and higher gross margins. This presentation will define embedded FPGA (eFPGA) technology, explain its potential benefits for SoC developers, and describe what to look for in a potential eFPGA IP partner.

                                        Itsu Wang

                                        Speakers and Exhibitors

                                        Look who you will meet at REUSE2017

                                        Sponsors and Partners


                                        Register for REUSE2017

                                        Registration is free and open to the entire semiconductor community.

                                        What the word on REUSE2017

                                        It’s great to see a show exclusively focused on semiconductor IP and the needs of the designers, REUSE is by far my favorite show.
                                        Mike Kaskowitzformer GM of IP at Mentor Graphics
                                        With its strong focus on Semiconductor IP, the REUSE Conference fills a void by providing an opportunity for IP vendors and chip designers to come together to exchange ideas and information.
                                        Jim LipmanMarketing Director, Sidense Corp.